uCsim, Copyright (C)  Daniel Drotos.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
# These are our test locations to be probed.
var loc1 rom[0x0000]
var loc2 rom[0x0001]

# Check the initial state of the default vcd.
info hw vcd
vcd[0] value change dump
  Modul:      ucsim_vcd_0
  Started:    no
  Paused:     no
  Mode:       output
  Time scale: auto set on start
  Start time: 0.000000000000000 s
  Last event: 0.000000000000000 s
  Pause time: 
  Simul time: 0.000000000000000 s
  Variables:
    Address           Symbol

# Run the initialization code and stop when we reach the
# first test loop.
break 0x800c
Breakpoint 1 at 0x00800c: 
0x0800c    <.loop$0>:
0x0800c F  72 10 00 00    bset   0x0000 <loc1>,#0 (cond="")
run
Simulation started, PC=0x008000

Stop at 0x00800c: (104) Breakpoint
V-IHINZC  Flags= 0x2a  42 *  A= 0x00   0 .
0-101010  X= 0x0000   0 .    Y= 0x0000   0 .
SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500

0x0800c    <.loop$0>:
0x0800c F  72 10 00 00    bset   0x0000 <loc1>,#0[0K
F 0x00800c
Simulated 8 ticks [ELIDED]
Host usage: [ELIDED]

# Set up a vcd to monitor the bit changes in loc1 and the value of loc2.
set hw vcd output "out/test.vcd"
set hw vcd add loc1.0
set hw vcd add loc1.1
set hw vcd add loc1.2
set hw vcd add loc1.3
set hw vcd add loc1.4
set hw vcd add loc1.5
set hw vcd add loc1.6
set hw vcd add loc1.7
set hw vcd add loc2
set hw vcd start

# Make sure what it is going to do is what we asked.
info hw vcd
vcd[0] value change dump
  Modul:      ucsim_vcd_0
  Started:    YES
  Paused:     no
  Mode:       output
  Time scale: 1 ns
  Start time: 0.000004000000000 s
  Last event: 0.000004000000000 s
  Pause time: 
  Simul time: 0.000004000000000 s
  Variables:
    Address           Symbol
    rom[0x00000].0    loc1.0
    rom[0x00000].1    loc1.1
    rom[0x00000].2    loc1.2
    rom[0x00000].3    loc1.3
    rom[0x00000].4    loc1.4
    rom[0x00000].5    loc1.5
    rom[0x00000].6    loc1.6
    rom[0x00000].7    loc1.7
    rom[0x00001]      loc2

# Run the first loop and stop when we hit the breakpoint again.
cont
Simulation started, PC=0x00800c

Stop at 0x00800c: (104) Breakpoint
V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500

0x0800c    <.loop$0>:
0x0800c F  72 10 00 00    bset   0x0000 <loc1>,#0[0K
F 0x00800c
Simulated 49 ticks [ELIDED]
Host usage: [ELIDED]

# Remove the probe from every second bit.
# Removing probes while started is ok - we just stop logging changes.
set hw vcd del loc1.1
set hw vcd del loc1.3
set hw vcd del loc1.5
set hw vcd del loc1.7

# We can't add anything though because that would require a change to the
# header and it's far too late for that.
set hw vcd add loc1.3
Already started

# Run the second loop and stop when we hit the breakpoint again.
cont
Simulation started, PC=0x00800c

Stop at 0x00800c: (104) Breakpoint
V-IHINZC  Flags= 0x28  40 (  A= 0x00   0 .
0-101000  X= 0x0000   0 .    Y= 0x0000   0 .
SP= 0x17ff [SP+1]= 00   0 .  Limit= 0x1500

0x0800c    <.loop$0>:
0x0800c F  72 10 00 00    bset   0x0000 <loc1>,#0[0K
F 0x00800c
Simulated 49 ticks [ELIDED]
Host usage: [ELIDED]

# Don't forget to close the vcd properly!
set hw vcd stop
